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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11257835 B1

PDFFull Text
Date of Patent:
Feb. 22, 2022

Filed:

Nov. 22, 2019

Three-dimensional memory device containing a dummy memory film isolation structure and method of making thereof

Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Liang Li, Shanghai, CN;

Chao Xu, Shanghai, CN;

Zhe Song, Shanghai, CN;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

The Marbury Law Group PLLC

Primary Examiner:

Nelson Garces

Int. Cl.
CPC ...
H01L 27/11565 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/11519 (2017.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 27/11582 (2017.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11565 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, rows of memory openings vertically extending through the alternating stack, memory opening fill structures located within a first subset of the rows of memory openings, where each of the memory opening fill structures includes a respective memory film and a respective vertical semiconductor channel extending through an opening at a bottom portion of the respective memory film and contacting a respective underlying semiconductor material portion, and dummy memory opening fill structures located within a second subset of the rows of memory openings that do not belong the first subset, where each of the dummy memory opening fill structures includes a respective dummy memory film and a respective dummy vertical semiconductor channel that is electrically isolated from a respective underlying semiconductor material portion by a bottom portion of the respective dummy memory film.

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