The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Jul. 02, 2020
Applicant:

Cambridge Enterprise Limited, Cambridge, GB;

Inventors:

Martin Arnold, Cambridge, GB;

Loizos Efthymiou, Cambridge, GB;

David Bruce Vail, Norfolk, GB;

John William Findlay, Cambridge, GB;

Giorgia Longobardi, Cambridge, GB;

Florin Udrea, Cambridge, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 49/02 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/872 (2006.01); H01L 21/8252 (2006.01); H01L 29/861 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0605 (2013.01); H01L 21/8252 (2013.01); H01L 27/0629 (2013.01); H01L 27/0883 (2013.01); H01L 28/20 (2013.01); H01L 28/40 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/7786 (2013.01); H01L 29/861 (2013.01); H01L 29/872 (2013.01); H01L 29/1066 (2013.01);
Abstract

The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.


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