The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2022
Filed:
Aug. 23, 2019
Applicant:
Toshiba Memory Corporation, Tokyo, JP;
Inventor:
Tomoya Sanuki, Yokkaichi Mie, JP;
Assignee:
Toshiba Memory Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 25/50 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/09181 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract
A semiconductor device includes: a first semiconductor substrate and a logic circuit provided on the first semiconductor substrate; a memory cell provided above the logic circuit and a second semiconductor substrate provided above the memory cell; a bonding pad provided above the second semiconductor substrate and electrically connected to the logic circuit; and a wiring provided above the second semiconductor substrate. The wiring is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.