The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Feb. 14, 2019
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken, JP;

Inventors:

Susumu Kawashima, Kanagawa, JP;

Kouhei Toyotaka, Kanagawa, JP;

Koji Kusunoki, Kanagawa, JP;

Kei Takahashi, Kanagawa, JP;

Kentaro Hayashi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/10 (2006.01); G09G 3/36 (2006.01); G09G 3/34 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3688 (2013.01); G09G 3/3413 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0235 (2013.01); G09G 2310/0262 (2013.01); G09G 2320/0242 (2013.01); G09G 2320/0252 (2013.01); H01L 29/786 (2013.01);
Abstract

A display device operating at high speed is provided. The display device includes a pixel provided with a first memory circuit, a second memory circuit, and a display unit, in which the first memory circuit and the second memory circuit are electrically connected to one electrode of the display unit. The operation of the display device includes a first period of writing first image data to the first memory circuit and writing second image data to the second memory circuit, a second period of supplying a first potential to the first memory circuit, a third period of displaying a first image corresponding to the first image data, a fourth period of setting a potential of the one electrode of the display unit to a second potential, a fifth period of supplying the first potential to the second memory circuit, and a sixth period of displaying a second image corresponding to the second image data.


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