The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2022
Filed:
Sep. 29, 2020
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Chuan Cheng Pan, San Jose, CA (US);
Hanh Hoang, Pleasanton, CA (US);
Chandrasekhar S. Thyamagondlu, Sunnyvale, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/24 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4081 (2013.01); G06F 13/24 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract
A method for managing a pool of physical functions in a PCIe integrated endpoint includes receiving a configuration instruction indicating a topology for a PCIe connected integrated endpoint (IE), and implementing the topology on the IE. The method further includes receiving a hot plug instruction, and, based at least in part, on the hot plug instruction, adding or removing a virtual endpoint (vEP) to or from a virtual downstream port (vDSP) on the IE.