The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Sep. 10, 2019
Applicant:

Arm Limited, Cambridge, GB;

Inventor:

Steven Douglas Krueger, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0846 (2016.01); G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 9/455 (2018.01); G06F 9/46 (2006.01); G06F 9/50 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0848 (2013.01); G06F 3/0622 (2013.01); G06F 3/0644 (2013.01); G06F 3/0653 (2013.01); G06F 3/0685 (2013.01); G06F 9/30101 (2013.01); G06F 9/45558 (2013.01); G06F 9/467 (2013.01); G06F 9/5016 (2013.01); G06F 9/5061 (2013.01); G06F 12/1009 (2013.01);
Abstract

Memory transactions can be tagged with a partition identifier selected depending on which software execution environment caused the memory transaction to be issued. A memory system component can control allocation of resources for handling the memory transaction or manage contention for said resources depending on a selected set of memory system component parameters selected depending on the partition identifier specified by the memory transaction, or can control, depending on the partition identifier specified by the memory transaction, whether performance monitoring data is updated in response to the memory transaction. Page table walk memory transactions may be assigned a different partition identifier to the partition identifier assigned to the corresponding data/instruction access memory transaction.


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