The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2022
Filed:
Dec. 29, 2017
Applicant:
Lightbits Labs Ltd., Kfar Saba, IL;
Inventors:
Shmuel Ben-Yehuda, Haifa, IL;
Ofir Efrati, Even Yehuda, IL;
Sagi Grimberg, Kfar Saba, IL;
Eran Kirzner, Moshav Elishama, IL;
Ziv Tishel, Kiryat Ono, IL;
Fabian Trumper, Sunnyvale, CA (US);
Assignee:
LIGHTBITS LABS LTD., Kfar Saba, IL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0637 (2013.01); G06F 3/068 (2013.01); G06F 3/0622 (2013.01); G06F 3/0653 (2013.01);
Abstract
A field programmable gate array (FPGA), that includes a trusted FPGA logic, an untrusted FPGA logic and a monitor; wherein the monitor is configured to monitor the untrusted FPGA logic and prevent the untrusted FPGA logic from violating predefined constrains imposed on an operation of the untrusted FPGA logic; wherein the predefined constraints are stored in a memory region of the FPGA that is not accessible to the untrusted FPGA logic.