The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2022
Filed:
Oct. 16, 2019
Cypress Semiconductor Corporation, San Jose, CA (US);
Mark Alan McClain, San Diego, CA (US);
Willy Obereiner, San Jose, CA (US);
Rainer Hoehler, Colorado Springs, CO (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
In an example embodiment, a device comprises a non-volatile memory and wear leveling control circuitry. The non-volatile memory comprises logical memory sectors mapped to physical memory sectors, and a supervisory memory sector configured to store a mapping of the logical memory sectors to memory partitions with user-defined boundaries. The wear leveling control circuitry is configured to: receive and store, in the mapping, wear leveling parameters based on user input, where each memory partition is associated with a wear leveling parameter indicating whether that memory partition is excluded from wear leveling; and determine and apply, to the non-volatile memory, wear leveling characteristics based on the wear leveling parameters, where the wear leveling characteristics identify an amount of wear leveling allowed for each of the memory partitions.