The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2022
Filed:
Feb. 17, 2020
Connection interface circuit, memory storage device and phase-locked loop circuit calibration method
Phison Electronics Corp., Miaoli, TW;
Chia-Hui Yu, Hsinchu County, TW;
Wun-Jian Su, New Taipei, TW;
Yu-Jung Chiu, Changhua County, TW;
Chiao-Chieh Yang, Hsinchu, TW;
PHISON ELECTRONICS CORP., Miaoli, TW;
Abstract
A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and calibrating an electrical parameter of the phase-locked loop circuit according to a variation of a time difference between the first signal and the third signal.