The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Jan. 21, 2020
Applicant:

Xsight Labs Ltd., Kiryat Gat, IL;

Inventors:

Carmi Arad, Nofit, IL;

Guy Koren, Rishon Lezion, IL;

Gal Malach, Gedera, IL;

Erez Shaizaf, Nir Chen, IL;

Assignee:

XSIGHT LABS LTD., Kiryat Gat, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/66 (2006.01); H01L 27/32 (2006.01); H04L 45/00 (2022.01); H04L 45/16 (2022.01); H01L 23/00 (2006.01); H04L 12/18 (2006.01); H01L 23/528 (2006.01); H04L 47/2425 (2022.01);
U.S. Cl.
CPC ...
H01L 27/3255 (2013.01); H01L 23/528 (2013.01); H01L 24/01 (2013.01); H04L 12/18 (2013.01); H04L 45/16 (2013.01); H04L 45/54 (2013.01); H04L 47/2433 (2013.01);
Abstract

A method for responding to a failure of a main die of a switch data-plane device, the method may include applying a secondary packet forwarding process by multiple chiplets, following the failure of the main die and during at least a part of an execution of a synchronous graceful process that follows the failure of the main die; wherein the multiple chiplets are interconnected to each other by a secondary interconnect; wherein the multiple chiplets and are coupled to the main die by a primary interconnect; wherein the applying of the secondary packet forwarding process is less complex than a primary forwarding process applied by the main die while the main die is functional.


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