The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Apr. 13, 2020
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yupeng Gao, Beijing, CN;

Guangcai Yuan, Beijing, CN;

Feng Guan, Beijing, CN;

Zhi Wang, Beijing, CN;

Jianhua Du, Beijing, CN;

Zhaohui Qiang, Beijing, CN;

Chao Li, Beijing, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 29/00 (2006.01); H01L 21/00 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/24 (2006.01); H01L 29/16 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1285 (2013.01); H01L 21/84 (2013.01); H01L 27/1225 (2013.01); H01L 27/1288 (2013.01); H01L 29/16 (2013.01); H01L 29/24 (2013.01); H01L 29/6675 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78675 (2013.01);
Abstract

The present disclosure discloses a method for preparing an array substrate, an array substrate and a display panel, wherein the method comprises: forming a buffer layer on a substrate in a first region and a second region, wherein the buffer layer has a groove located in the second region; forming a first indium oxide thin film on the buffer layer in the first region; forming a second indium oxide thin film in the groove; performing a reduction process on the second indium oxide thin film to obtain indium particles; forming an amorphous silicon thin film in the groove, and inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles; and removing the indium particles in the microcrystalline silicon to form a microcrystalline silicon semiconductor layer of the microcrystalline silicon thin film transistor.


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