The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2022
Filed:
Nov. 20, 2019
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 23/538 (2006.01); H01L 23/522 (2006.01); H01L 23/498 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 29/42392 (2013.01); H01L 29/785 (2013.01);
Abstract
Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.