The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Sep. 01, 2017
Applicant:

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Philippe Galy, Le Touvet, FR;

Thomas Bedecarrats, Saint Martin d'heres, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/04 (2006.01); G06N 3/063 (2006.01); H01L 27/02 (2006.01); G11C 11/54 (2006.01); H01L 29/423 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
G06N 3/04 (2013.01); G06N 3/049 (2013.01); G06N 3/063 (2013.01); G06N 3/0635 (2013.01); G11C 11/54 (2013.01); H01L 27/027 (2013.01); H01L 27/0285 (2013.01); H01L 29/42376 (2013.01); H03K 3/356 (2013.01);
Abstract

An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.


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