The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2022
Filed:
Sep. 05, 2019
Nvidia Corporation, Santa Clara, CA (US);
Jerome F. Duluk, Jr., Palo Alto, CA (US);
Gregory Scott Palmer, Cedar Park, TX (US);
Jonathon Stuart Ramsey Evans, Santa Clara, CA (US);
Shailendra Singh, Fremont, CA (US);
Samuel H. Duncan, Arlington, MA (US);
Wishwesh Anil Gandhi, Sunnyvale, CA (US);
Lacky V. Shah, Los Altos, CA (US);
Eric Rock, San Jose, CA (US);
Feiqi Su, Cupertino, CA (US);
James Leroy Deming, Madison, AL (US);
Alan Menezes, San Jose, CA (US);
Pranav Vaidya, San Jose, CA (US);
Praveen Joginipally, San Jose, CA (US);
Timothy John Purcell, Melbourne, AU;
Manas Mandal, Palo Alto, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.