The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Feb. 10, 2020
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Dong Lim Kim, Suwon-si, KR;

Je Hyeong Park, Seoul, KR;

Kyoung-Jun Kim, Hwaseong-si, KR;

Yu-Jin Kim, Asan-si, KR;

Chang Young Kim, Asan-si, KR;

Ji Hyun Min, Bucheon-si, KR;

Min Hee Son, Anyang-si, KR;

Hyoung Wook Song, Cheonan-si, KR;

Chan Young Lim, Cheonan-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1335 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136227 (2013.01); G02F 1/1368 (2013.01); G02F 1/133512 (2013.01); G02F 1/133514 (2013.01); G02F 1/136286 (2013.01); H01L 27/124 (2013.01); H01L 27/1248 (2013.01); G02F 1/136222 (2021.01);
Abstract

A display device according to an embodiment includes: a substrate; and a plurality of pixels, the plurality of pixels including a first pixel, a second pixel and a third pixel. Each of the plurality of pixels including a gate line extends in a first direction; a first transistor and a second transistor connected with the gate line; a pixel electrode that includes a first subpixel electrode and a second subpixel electrode; a first bridge that connects the first subpixel electrode and the first transistor; and a second bridge that connects the second subpixel electrode and the second transistor. At least one of the second pixel and the third pixel includes a light blocking pattern that overlaps at least one of the first transistor and the second transistor. The first bridge and the second bridge do not overlap or cross the light blocking pattern in a plan view.


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