logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11244732 B1

PDFFull Text
Date of Patent:
Feb. 08, 2022

Filed:

Mar. 26, 2019

Single page read level tracking by bit error rate analysis

Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Eran Sharon, San Jose, CA (US);

Alex Bazarsky, San Jose, CA (US);

Idan Alrod, San Jose, CA (US);

Assignee:

Western Digital Technologies, Inc., San Jose, CA (US);

Attorneys:

Dickinson Wright PLLC

Steven Hurles

Primary Examiner:

Khamdan N Alrobaie

Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G11C 11/56 (2006.01); G06F 11/07 (2006.01); G11C 7/14 (2006.01); G11C 16/28 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3404 (2013.01); G06F 11/076 (2013.01); G11C 7/14 (2013.01); G11C 11/5642 (2013.01); G11C 16/28 (2013.01); G11C 16/3445 (2013.01); G11C 16/3495 (2013.01); G11C 29/028 (2013.01); G11C 29/50004 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A method for calibrating read threshold voltages includes receiving, from at least one memory die, a number of page bits corresponding to a number of read operations performed on a page associated with the at least one memory die. The method further includes determining voltage bins for each bit of the number of page bits. The method further includes determining, for each voltage bin, a bit error rate. The method further includes adjusting read threshold voltages associated with the at least one memory die using the bite error rate for each voltage bin.

Find Patent Forward Citations

Quick Actions:

Sharon, Eran. (2022). Single page read level tracking by bit error rate analysis (U.S. Patent No. 11244732). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11244732

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…