The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Apr. 04, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Steven Craig Bartling, Plano, TX (US);

Sudhanshu Khanna, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G06F 3/06 (2006.01); H03K 3/3562 (2006.01); G06F 11/10 (2006.01); G06F 11/14 (2006.01); G06F 12/02 (2006.01); G06F 9/4401 (2018.01); G06F 1/3203 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 13/00 (2006.01); G11C 14/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G06F 1/3203 (2013.01); G06F 1/3234 (2013.01); G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G06F 9/4401 (2013.01); G06F 9/4406 (2013.01); G06F 11/1032 (2013.01); G06F 11/1438 (2013.01); G06F 11/1469 (2013.01); G06F 12/0238 (2013.01); G06F 13/00 (2013.01); G11C 14/00 (2013.01); H03K 3/3562 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08);
Abstract

Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.


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