The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Aug. 13, 2019
Applicant:

Netlist, Inc., Irvine, CA (US);

Inventors:

Hyun Lee, Ladera Ranch, CA (US);

Jayesh R Bhakta, Cerritos, CA (US);

Chi She Chen, Walnut, CA (US);

Jeffery C. Solomon, Irvine, CA (US);

Mario Jesus Martinez, Laguna Niguel, CA (US);

Hao Le, Santa Ana, CA (US);

Soon J. Choi, Irvine, CA (US);

Assignee:

Netlist, Inc., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0871 (2016.01); G06F 3/06 (2006.01); G06F 12/0897 (2016.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0871 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 12/0897 (2013.01); G06F 13/28 (2013.01); G06F 2206/1014 (2013.01); G06F 2212/214 (2013.01); G06F 2212/313 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7208 (2013.01);
Abstract

A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.


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