The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

May. 30, 2019
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Tatsuya Iwamoto, Foster City, CA (US);

Jason P. Jane, San Jose, CA (US);

Rohan Sanjeev Patil, San Francisco, CA (US);

Kutty Banerjee, San Jose, CA (US);

Subodh Asthana, Sunnyvale, CA (US);

Kyle J. Haughey, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06T 1/20 (2006.01); G06F 17/18 (2006.01); G06F 1/3228 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3243 (2013.01); G06F 1/3228 (2013.01); G06F 1/3287 (2013.01); G06F 17/18 (2013.01); G06T 1/20 (2013.01);
Abstract

Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.


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