Networks and hierarchical routing fabrics with heterogeneous memory structures for scalable event-driven computing systems

Abstract

Among other aspects, the present invention relates to a network comprising a plurality of interconnected core circuits () particularly arranged on several units (), wherein each core circuit () comprises: an electronic array () comprising a plurality of computing nodes () and a plurality of memory circuits () which is configured to receive incoming events, wherein each computing node () is configured to generate an event comprising a data packet when incoming events received by the respective computing node () satisfy a pre-defined criterion, and a circuit which is configured to append destination address and additional source information, particularly source core ID, to the respective data packet, and a local first router (R) for providing intra-core connectivity and/or delivering events to intermediate level second router (R) for inter-core connectivity and to higher level third router (R) for inter-unit connectivity, and a broadcast driver () for broadcasting incoming events to all the memory circuits () in the core circuit () in parallel.