Multi-level circuit, three-phase multi-level circuit, and control method

Abstract

A multi-level circuit, a three-phase multi-level circuit, and a control method are provided. The multi-level circuit includes two groups of bus capacitors (Cand C) that are connected in series; a plurality of switching transistor branches that are connected in parallel to the capacitors, where each switching transistor branch includes a first half bridge (Qand Q) and a second half bridge (Qand Q), and a common terminal of the two half bridges is grounded (N); and two negative coupled inductors (Land L), where each input terminal of each negative coupled inductor is connected to a common terminal (Aand A) of two switching transistors in the first half bridge in only one of the switching transistor branches. In this circuit, a quantity of groups of bus capacitors is decreased and circuit design complexity is reduced. Further, a dropout voltage of the switching transistors is reduced.