The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Jan. 11, 2019
Applicant:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Inventors:

Keum Ju Lee, Ansan-si, KR;

Seom Geun Lee, Ansan-si, KR;

Kyoung Wan Kim, Ansan-si, KR;

Yong Woo Ryu, Ansan-si, KR;

Mi Na Jang, Ansan-si, KR;

Assignee:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/14 (2010.01); H01L 33/38 (2010.01); H01L 33/06 (2010.01); H01L 27/15 (2006.01); H01L 33/10 (2010.01); H01L 33/32 (2010.01); H01L 33/42 (2010.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 33/145 (2013.01); H01L 27/15 (2013.01); H01L 27/156 (2013.01); H01L 33/06 (2013.01); H01L 33/10 (2013.01); H01L 33/32 (2013.01); H01L 33/38 (2013.01); H01L 33/42 (2013.01); H01L 33/62 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01);
Abstract

A light emitting diode includes: a substrate; a semiconductor stack disposed on the substrate and including a lower semiconductor layer, an upper semiconductor layer and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, the semiconductor stack having an isolation groove exposing the substrate through the upper semiconductor layer, the active layer and the lower semiconductor layer; a first electrode pad and an upper extension portion electrically connected to the upper semiconductor layer; a second electrode pad and a lower extension portion electrically connected to the lower semiconductor layer; a connecting portion connecting the upper extension portion and the lower extension portion to each other across the isolation groove; a first current blocking layer interposed between the lower extension portion and the lower semiconductor layer; and a second current blocking layer interposed between the second electrode pad and the lower semiconductor layer.


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