The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Sep. 27, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Vladislav Komenko, Dresden, DE;

Heiko Froehlich, Radebeul, DE;

Thoralf Kautzsch, Dresden, DE;

Andrey Kravchenko, Dresden, DE;

Bernhard Winkler, Regensburg, DE;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/84 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/84 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 21/26513 (2013.01); H01L 21/28568 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/324 (2013.01); H01L 21/762 (2013.01); H01L 29/0653 (2013.01); H01L 2924/13072 (2013.01);
Abstract

A method for manufacturing a pressure sensitive transistor includes forming a channel region between first and second contact regions in a semiconductor substrate, forming a first isolation layer on a surface of the semiconductor substrate, forming a sacrificial structure on the first isolation layer and above the channel region, forming a semiconductor layer on the sacrificial structure and on the first isolation layer, wherein the semiconductor layer covers the sacrificial structure, removing the sacrificial structure for providing a cavity between the substrate and the semiconductor layer, wherein the semiconductor layer forms a membrane structure and forms a control electrode of the pressure sensitive transistor, forming a second isolation layer on the membrane structure and on the exposed portion of the surface of the semiconductor substrate, and forming contacting structures for the first contact region, the second contact region and the membrane structure of the pressure sensitive transistor.


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