The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Mar. 03, 2020
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventors:

Shoichi Watanabe, Kawasaki, JP;

Mitsuhiro Noguchi, Yokohama, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 27/092 (2006.01); H01L 27/11573 (2017.01); H01L 29/34 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 27/11582 (2017.01); H01L 27/11551 (2017.01); H01L 27/1157 (2017.01); H01L 27/11524 (2017.01); H01L 27/11578 (2017.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); G11C 16/30 (2013.01); H01L 21/823418 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 27/0922 (2013.01); H01L 27/11573 (2013.01); H01L 29/34 (2013.01);
Abstract

According to a certain embodiment, the nonvolatile semiconductor memory device includes: a first conductivity-type semiconductor substrate including a crushed layer on a back side surface thereof; a memory cell array disposed on a front side surface of the semiconductor substrate opposite to the crushed layer; and a first conductivity-type high voltage transistor HVP disposed on the semiconductor substrate and including a first conductivity-type channel, configured to supply a high voltage to the memory cell array. The first conductivity-type high voltage transistor includes: a well region NW disposed on the surface of the semiconductor substrate and having a second conductivity type; a source region and a drain region disposed in the well region; and a first conductivity-type first high concentration layer WTdisposed between the crushed layer of the semiconductor substrate and the well region and having a higher concentration than an impurity concentration of the semiconductor substrate.


Find Patent Forward Citations

Loading…