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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11239314 B1

PDFFull Text
Date of Patent:
Feb. 01, 2022

Filed:

Feb. 01, 2019

Semiconductor device and method of manufacturing the same

Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Masahiro Masunaga, Tokyo, JP;

Akio Shima, Tokyo, JP;

Shintaroh Sato, Tokyo, JP;

Ryo Kuwana, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:

Volpe Koenig

Primary Examiner:

Moin M Rahman

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 23/535 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/16 (2006.01); H01L 29/45 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0653 (2013.01); H01L 23/535 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/41758 (2013.01); H01L 29/45 (2013.01); H01L 29/66068 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/02378 (2013.01); H01L 21/02529 (2013.01); H01L 21/02634 (2013.01); H01L 21/046 (2013.01); H01L 21/049 (2013.01); H01L 21/0485 (2013.01); H01L 29/78 (2013.01);
Abstract

A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.

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