The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2022
Filed:
Apr. 20, 2020
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Dong-Soo Kim, Gyeonggi-do, KR;
Se-Han Kwon, Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 27/108 (2006.01); H01L 29/417 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823418 (2013.01); H01L 21/76877 (2013.01); H01L 21/823468 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 29/41783 (2013.01); H01L 29/4236 (2013.01);
Abstract
A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.