The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Mar. 27, 2020
Applicant:

Huawei Technologies Co., Ltd., Guangdong, CN;

Inventors:

Shifeng Xu, Shanghai, CN;

Xi Chen, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/177 (2006.01); G06F 21/57 (2013.01); G06F 9/4401 (2018.01); G06F 21/44 (2013.01); G06F 21/60 (2013.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G06F 21/575 (2013.01); G06F 9/4401 (2013.01); G06F 21/44 (2013.01); G06F 21/602 (2013.01); G11C 11/412 (2013.01); G06F 9/4406 (2013.01);
Abstract

One example method includes copying code and a security signature of a first off-chip boot to a static random access memory (SRAM) for signature verification, where a function implemented by the first off-chip boot includes initializing a double data rate synchronous dynamic random access memory (DDR), and the DDR initialization includes configuring a DDR secure zone, executing, in the SRAM, the code of the first off-chip boot after the signature verification on the first off-chip boot succeeds to initialize the DDR and configure the DDR secure zone, copying code and a security signature of a second off-chip boot to the DDR secure zone for signature verification, where the second off-chip boot is all of other boots in off-chip boots except the first off-chip boot, and executing, in the DDR secure zone, the code of the second off-chip boot after the signature verification on the second off-chip boot succeeds.


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