The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Jan. 16, 2020
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Zehan Cui, Beijing, CN;

Mingyu Chen, Beijing, CN;

Yao Liu, Beijing, CN;

Yuan Ruan, Beijinig, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0608 (2013.01); G06F 3/06 (2013.01); G06F 3/065 (2013.01); G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 12/0623 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01); G06F 13/1694 (2013.01); G06F 13/4234 (2013.01); G06F 12/0215 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1024 (2013.01); G06F 2213/0064 (2013.01);
Abstract

In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.


Find Patent Forward Citations

Loading…