The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Dec. 04, 2018
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Rihoko Watanabe, Osaka, JP;

Keiko Kashihara, Osaka, JP;

Hiroharu Inoue, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H05K 1/03 (2006.01); H01L 23/12 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/03 (2013.01); H01L 23/12 (2013.01); H01L 23/3128 (2013.01); H01L 24/16 (2013.01);
Abstract

A prepreg is used to fabricate a semiconductor package including a chip and a substrate to mount the chip thereon. The prepreg is in a semi-cured state. The substrate includes a cured product of the prepreg. The chip has: a first chip surface located opposite from the substrate; and a second chip surface located opposite from the first chip surface. The prepreg satisfies the relational expression: 0.9≤X/X≤1.0 (I), where Xis a coefficient of thermal expansion of the first chip surface of the chip before the chip is mounted on the substrate, and Xis a coefficient of thermal expansion of the first chip surface of the chip after the chip has been mounted on the substrate.


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