The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Jan. 28, 2019
Applicant:

Oepic Semiconductors, Inc, Sunnyvale, CA (US);

Inventor:

Yi-Ching Pao, Sunnyvale, CA (US);

Assignee:

OEPIC SEMICONDUCTORS INC., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/183 (2006.01); H01S 5/42 (2006.01); H01S 5/0234 (2021.01); H01S 5/042 (2006.01); H01S 5/026 (2006.01); H01S 5/0237 (2021.01); H01S 5/02345 (2021.01);
U.S. Cl.
CPC ...
H01S 5/18369 (2013.01); H01S 5/0234 (2021.01); H01S 5/18305 (2013.01); H01S 5/18341 (2013.01); H01S 5/423 (2013.01); H01S 5/026 (2013.01); H01S 5/0237 (2021.01); H01S 5/02345 (2021.01); H01S 5/04254 (2019.08); H01S 5/18388 (2013.01); H01S 2301/176 (2013.01);
Abstract

A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.


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