The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Mar. 24, 2020
Applicant:

Newport Fab, Llc, Newport Beach, CA (US);

Inventors:

Edward Preisler, San Clemente, CA (US);

Zhirong Tang, Lake Oswego, OR (US);

Assignee:

Newport Fab, LLC, Newport Beach, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/02 (2006.01); H01L 31/18 (2006.01); H01L 31/0304 (2006.01); H01L 31/109 (2006.01); H01S 5/02 (2006.01);
U.S. Cl.
CPC ...
H01L 31/02005 (2013.01); H01L 31/03046 (2013.01); H01L 31/109 (2013.01); H01L 31/1844 (2013.01); H01S 5/021 (2013.01); H01S 5/0218 (2013.01);
Abstract

In fabricating a semiconductor structure, a group IV substrate and a group III-V chiplet are provided. The group III-V chiplet is bonded to the group IV substrate, and patterned to produce a patterned group III-V device. A blanket dielectric layer is formed over the patterned group III-V device. A first contact hole is formed in the blanket dielectric layer over a first portion of the patterned group III-V device. A first liner stack and a first filler metal are subsequently formed in the first contact hole. A second contact hole is formed in the blanket dielectric layer over a second portion of the patterned group III-V device. A second liner stack and a second filler metal are subsequently formed in the second contact hole. A first bottom metal liner of the first liner stack can be different from a second bottom metal liner of the second liner stack.


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