The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Jan. 16, 2019
Applicant:

Ipower Semiconductor, Gilroy, CA (US);

Inventor:

Hamza Yilmaz, Gilroy, CA (US);

Assignee:

IPOWER SEMICONDUCTOR, Gilroy, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 21/306 (2006.01); H01L 21/266 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/732 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7397 (2013.01); H01L 21/0209 (2013.01); H01L 21/266 (2013.01); H01L 21/30604 (2013.01); H01L 29/0619 (2013.01); H01L 29/0623 (2013.01); H01L 29/0661 (2013.01); H01L 29/0821 (2013.01); H01L 29/0834 (2013.01); H01L 29/1095 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01); H01L 29/417 (2013.01); H01L 29/66348 (2013.01); H01L 29/7396 (2013.01); H01L 29/7802 (2013.01); H01L 29/0638 (2013.01); H01L 29/0692 (2013.01); H01L 29/4238 (2013.01); H01L 29/732 (2013.01); H01L 2224/49175 (2013.01);
Abstract

A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.


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