The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Dec. 11, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ki Hyun Kim, Hwaseong-si, KR;

Seung Wan Hong, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11578 (2017.01); H01L 27/11582 (2017.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 27/11565 (2017.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 29/792 (2006.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0223 (2013.01); H01L 21/02271 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/42368 (2013.01); H01L 29/4991 (2013.01); H01L 29/513 (2013.01); H01L 29/7926 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 27/11575 (2013.01);
Abstract

The semiconductor device includes interlayer insulating layers, a gate pattern and a vertical memory structure. The interlayer insulating layers are stacked on the substrate to be spaced apart from each other. The gate pattern includes an overlapping portion disposed vertically between the interlayer insulating layers, and an extension portion extending from the overlapping portion in a horizontal direction parallel to an upper surface of the substrate. The vertical memory structure includes a channel semiconductor layer and a dielectric structure, the channel semiconductor layer extends in a direction perpendicular to the substrate upper surface to have side surfaces that face side surfaces of the interlayer insulating layers and a side surface of the extension portion. The dielectric structure is disposed between the channel semiconductor layer and the gate pattern and extends between the channel semiconductor layer and the interlayer insulating layers, and the extension portion has a vertical thickness less than that of the overlapping portion.


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