The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Sep. 28, 2020
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Hiroshi Kanno, Matsumoto, JP;

Masaharu Yamaji, Matsumoto, JP;

Hitoshi Sumida, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 23/00 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H02M 1/08 (2006.01); H01L 21/8238 (2006.01); H01L 21/761 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0921 (2013.01); H01L 24/48 (2013.01); H01L 29/0623 (2013.01); H01L 29/0638 (2013.01); H01L 29/1083 (2013.01); H01L 21/761 (2013.01); H01L 21/823892 (2013.01); H01L 29/0692 (2013.01); H01L 29/1087 (2013.01); H02M 1/08 (2013.01);
Abstract

A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.


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