The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Jun. 30, 2017
Applicant:

Rockwell Collins, Inc., Cedar Rapids, IA (US);

Inventors:

Brandon C. Hamilton, Marion, IA (US);

Kyle B. Snyder, Marion, IA (US);

Alan P. Boone, Swisher, IA (US);

Assignee:

Rockwell Collins, Inc., Cedar Rapids, IA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/85 (2013.01); H01L 24/92 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/4807 (2013.01); H01L 2224/4809 (2013.01); H01L 2224/48101 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48997 (2013.01); H01L 2224/48998 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/85007 (2013.01); H01L 2224/92247 (2013.01); H01L 2225/0651 (2013.01);
Abstract

An electrical device with printed interconnects between packaged integrated circuit components and a substrate as well as a method for printing interconnects between packaged integrated circuit components and a substrate are disclosed. An electrical device with printed interconnects may include a dielectric layer forming a continuous surface between a substrate and a terminal face of an integrated circuit component. The electrical device may further include interconnects formed from a layer of material printed across the continuous surface formed by the dielectric layer to connect electrical terminals on the substrate to electrical terminals on the terminal face of the integrated circuit component.


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