The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Feb. 16, 2020
Applicant:

Silergy Semiconductor Technology (Hangzhou) Ltd, Hangzhou, CN;

Inventor:

Jiaming Ye, Hangzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 21/4853 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/3128 (2013.01); H01L 23/49541 (2013.01); H01L 23/5389 (2013.01); H01L 24/09 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 23/49816 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/12105 (2013.01); H01L 2924/18162 (2013.01);
Abstract

The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant surrounding the chip to have an increased area. A redistribution layer is formed on the package unit to draw out to and redistribute input/output terminals on a surface of the chip. The redistribution layer is then electrically coupled to a leadframe or a printed circuit board by external and electrical connectors. The method and the package structure are suitable for providing a chip package having input/output terminals with high density, reducing package cost, and improving package reliability.


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