The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Oct. 29, 2019
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Wesley James Holland, Encinitas, CA (US);

Mehrad Tavakoli, San Diego, CA (US);

Injoon Hong, San Diego, CA (US);

Huang Huang, San Diego, CA (US);

Simon Peter William Booth, San Diego, CA (US);

Gerhard Reitmayr, Del Mar, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3287 (2019.01); G06F 3/01 (2006.01); G06F 3/14 (2006.01); G06T 5/00 (2006.01); G06T 19/00 (2011.01); G11C 11/419 (2006.01); G11C 11/412 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G06F 1/3287 (2013.01); G06F 3/013 (2013.01); G06F 3/14 (2013.01); G06T 5/006 (2013.01); G06T 19/006 (2013.01); G11C 11/412 (2013.01); H01L 27/1104 (2013.01);
Abstract

Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.


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