The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Sep. 12, 2019
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Naoya Okamura, Tokyo, JP;

Takumi Tsujishita, Tokyo, JP;

Masanori Fujii, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 21/55 (2013.01); G06F 13/10 (2006.01); G06F 21/57 (2013.01);
U.S. Cl.
CPC ...
G06F 21/554 (2013.01); G06F 13/102 (2013.01); G06F 21/575 (2013.01); G06F 2221/034 (2013.01);
Abstract

In a storage system including an FPGA having a logic which executes a prescribed processing and a plurality of devices coupled to the FPGA via a bus, the logic of the FPGA is configured to: attempt to access the plurality of devices and, based on a status of access to the devices, determine whether or not there is an abnormality in the access to the devices; and when it is determined that there is an abnormality in the access to a device, reset an IF unit for performing a communication processing via a bus of the device.


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