The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Apr. 07, 2020
Applicant:

Eidetic Communications Inc., Calgary, CA;

Inventors:

Stephen Bates, Canmore, CA;

Saeed Fouladi Fard, Calgary, CA;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 11/14 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/065 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A method, a hardware accelerator, and a system for performing computational storage utilizing a hardware accelerator device that includes a dedicated buffer memory residing on the hardware accelerator device and is connected to a central processing unit (CPU) via a bus includes receiving, at the hardware accelerator device, computation data from the CPU computing device via the bus, performing, at the hardware accelerator device, a check pointing operation on the received computation data to generate check point data, storing the generated check point data on the dedicated buffer memory residing on the hardware accelerator device, and transmitting the check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU.


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