The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Jul. 07, 2020
Applicant:

Cirrus Logic International Semiconductor, Ltd., Edinburgh, GB;

Inventors:

Chandra Prakash, Austin, TX (US);

Prashanth Drakshapalli, Austin, TX (US);

Assignee:

CIRRUS LOGIC, INC., Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/46 (2006.01); H02J 7/34 (2006.01);
U.S. Cl.
CPC ...
G05F 1/468 (2013.01); H02J 7/345 (2013.01);
Abstract

A power managed voltage reference quickly provides accurate operation when enabled and also avoids back-charging power supply rails when disabled. When disabled, the voltage reference filter capacitor is decoupled from the voltage reference buffer and coupled to a pre-charge source having a voltage magnitude greater than the reference voltage. When the voltage reference is enabled, the capacitor is coupled to a discharge path and the voltage across the capacitor is detected to determine when to decouple the capacitor from the discharge path and couple the capacitor to the voltage reference buffer. The capacitor voltage is also detected while disabling the voltage reference. Back-charging the pre-charge supply is prevented by coupling the capacitor to the discharge path until the magnitude of the capacitor voltage is less than the lowest voltage specified for the pre-charge supply, then coupling the capacitor to the pre-charge supply to prepare for enabling the voltage reference.


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