The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2022

Filed:

Mar. 19, 2020
Applicant:

Juniper Networks, Inc., Sunnyvale, CA (US);

Inventor:

John Ferullo, Sunnyvale, CA (US);

Assignee:

Juniper Networks, Inc, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 9/00 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H05K 2201/10227 (2013.01);
Abstract

The disclosed interference-fit frame includes (1) a border dimensioned for installation around an electrical component coupled to a circuit board, wherein (A) the border forms an opening in which the electrical component resides when the border is installed and (B) at least a portion of the border constitutes a retention dam that rises beyond the electrical component when the border is installed, and (2) at least one protuberance that extends from the border into the opening. Various other apparatuses, systems, and methods are also disclosed.


Find Patent Forward Citations

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Ferullo, John. (2022). Apparatus, system, and method for retaining thermal interface material between electrical components and heatsinks (U.S. Patent No. 11229120). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11229120

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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