The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2022

Filed:

Jan. 02, 2018
Applicants:

Sharp Kabushiki Kaisha, Sakai, JP;

Fg Innovation Company Limited, Hong Kong, CN;

Inventors:

Jia Sheng, Vancouver, WA (US);

Tatsushi Aiba, Vancouver, WA (US);

Toshizo Nogami, Vancouver, WA (US);

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04W 48/10 (2009.01); H04W 56/00 (2009.01); H04L 27/26 (2006.01); H04J 11/00 (2006.01); H04W 48/12 (2009.01); H04L 5/00 (2006.01);
U.S. Cl.
CPC ...
H04W 48/10 (2013.01); H04J 11/0073 (2013.01); H04J 11/0076 (2013.01); H04L 27/2613 (2013.01); H04L 27/2692 (2013.01); H04W 56/001 (2013.01); H04L 5/0053 (2013.01); H04L 27/26 (2013.01); H04W 48/12 (2013.01);
Abstract

An access node comprises node processor circuitry and a node transmitter. The node processor circuitry is configured to generate plural types of synchronization signal blocks for at least partially interspersed transmission over a radio interface. Each synchronization signal block type comprises a unique combination of differing types of information. The node transmitter circuitry configured to at least partially intersperse transmission of the plural types of synchronization signal blocks over the radio interface to at least one wireless terminal. The wireless terminal comprises a terminal receiver and terminal processor circuitry. The terminal receiver is configured to receive, in at least partially interspersed manner, synchronization signal blocks of differing types over a radio interface from an access node. The terminal processor circuitry is configured determine to which of plural types of synchronization signal blocks a received synchronization signal block belongs.


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