The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2022

Filed:

Jul. 06, 2018
Applicant:

Truly (Huizhou) Smart Display Limited, Guangdong, CN;

Inventors:

Koji Suzuki, Guangdong, CN;

Zhuo Chen, Guangdong, CN;

Yixian Zhang, Guangdong, CN;

Fan Zhang, Guangdong, CN;

Siyu Ren, Guangdong, CN;

Junhai Su, Guangdong, CN;

Jianhua Li, Guangdong, CN;

Assignee:

Other;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/3213 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/127 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/32136 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1259 (2013.01); H01L 27/1262 (2013.01); H01L 29/4908 (2013.01); H01L 29/66757 (2013.01); H01L 29/78675 (2013.01);
Abstract

Disclosed in the present invention are a method for manufacturing a thin-film transistor, an array substrate, and a display device. The method includes: forming a buffer layer on a substrate; forming a polysilicon layer on the buffer layer; performing a patterning process on the polysilicon layer, to form an active layer; depositing a gate insulating layer on the active layer; depositing a gate metal layer on the gate insulating layer, and performing dry etching on the gate metal layer by using the patterning process and by using a gas containing CO as an etching gas, to form a gate; performing ion implantation on the active layer by using the gate as a mask, to form a source region and a drain region; and depositing a passivation layer on the gate, forming through holes in the gate insulating layer and the passivation layer, and manufacturing a source and a drain.


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