The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2022

Filed:

Aug. 13, 2020
Applicant:

Tianma Microelectronics Co., Ltd., Shenzhen, CN;

Inventor:

Kazushige Takechi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1251 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 27/3262 (2013.01);
Abstract

A semiconductor device includes an insulating substrate, a polysilicon layer formed on the insulating substrate, a first-gate-insulating layer formed on the polysilicon layer, a first metal layer formed on the first-gate-insulating layer, an oxide-semiconductor layer formed on the first-gate-insulating layer, a second-gate-insulating layer formed on the oxide-semiconductor layer, a second metal layer formed on the second-gate-insulating layer, a first insulating interlayer formed on the second metal layer, a third metal layer formed on the first insulating interlayer, a first top gate planar type thin film transistor in which the polysilicon layer serves as a channel and which has a source, a drain and a gate, and a second top gate planar self-aligned type thin film transistor in which the oxide-semiconductor layer serves as a channel and which has a source, a drain and a gate, wherein the gate of the first top gate planar type thin film transistor is made of a first metal layer, the gate of the second top gate planar self-aligned type thin film transistor is made of the second metal layer, the source and the drain of the first top gate planar type thin film transistor and the source and the drain of the second top gate planar self-aligned type thin film transistor are made of the third metal layer, and the source or the drain of the first top gate planar type thin film transistor and the gate of the second top gate planar self-aligned type thin film transistor are electrically connected to each other.


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