The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2022
Filed:
Jul. 21, 2020
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
John Laurence Pennock, Juniper Green, GB;
John Paul Lesso, Edinburgh, GB;
Cirrus Logic, Inc., Austin, TX (US);
Abstract
This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit () includes a first MOS device () and a bias controller (). The circuit is operable in at least a first circuit state (P) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V, V) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.