The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Jan. 29, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Amarnath Kasibhatla, San Jose, CA (US);

Saurabh Mathur, Saratoga, CA (US);

Mansi Shrikant Patwardhan, San Jose, CA (US);

Tim Tuan, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/28 (2006.01); G06F 1/04 (2006.01); H03K 17/00 (2006.01);
U.S. Cl.
CPC ...
H03K 17/28 (2013.01); G06F 1/04 (2013.01); H03K 17/002 (2013.01);
Abstract

A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports or the state of the one or more output ports change upon determining the states have been stable for the preset number of the cycles.


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