The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Aug. 14, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Raheel Azmat, Suwon-si, KR;

Jaehyoung Lim, Anyang-si, KR;

Taehyung Kim, Hwaseong-si, KR;

Jinwoo Jeong, Suwon-si, KR;

Jaeseok Yang, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); G01R 31/3177 (2013.01); G01R 31/31704 (2013.01); G01R 31/31723 (2013.01);
Abstract

A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.


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