The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Dec. 19, 2019
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Karri Rajesh, Visakhapatnam, IN;

Arun Khamesra, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/335 (2006.01); H02M 1/00 (2006.01); H02M 1/08 (2006.01); H02M 1/34 (2007.01); H02J 7/00 (2006.01);
U.S. Cl.
CPC ...
H02M 1/0029 (2021.05); H02M 1/08 (2013.01); H02M 3/33523 (2013.01); H02M 3/33592 (2013.01); H02J 7/0045 (2013.01); H02J 2207/20 (2020.01); H02M 1/34 (2013.01);
Abstract

A synchronous switching scheme with adaptive slew control in order to adiabatically charge and discharge a capacitor to recycle charge and generate a boosted voltage on the gate of the synchronous rectifier field effect transistor (FET) is described. In one embodiment, an apparatus includes a synchronous rectifier FET coupled to a transformer, and a secondary-side controller coupled to the synchronous rectifier FET. The secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to a gate of the synchronous rectifier FET. The SRGD is to drive the synchronous rectifier FET using the capacitor and an adaptive slew rate, and to adiabatically charge and discharge the capacitor.


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