The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2022
Filed:
May. 20, 2016
Applicant:
Hrl Laboratories Llc, Malibu, CA (US);
Inventors:
Jeong-Sun Moon, Moorpark, CA (US);
Hwa Chang Seo, Torance, CA (US);
Assignee:
HRL Laboratories, LLC, Malibu, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66045 (2013.01); H01L 21/0228 (2013.01); H01L 21/0234 (2013.01); H01L 21/02164 (2013.01); H01L 21/02181 (2013.01); H01L 21/02359 (2013.01); H01L 29/1606 (2013.01); H01L 29/4908 (2013.01); H01L 29/517 (2013.01); H01L 29/66015 (2013.01); H01L 29/78684 (2013.01); H01L 2924/13088 (2013.01);
Abstract
A Field Effect Transistor (FET) device and a method for manufacturing it are disclosed. The FET device contains a graphene layer, a composite gate dielectric layer disposed above the graphene layer, wherein the composite gate layer is passivated with fluorine, and a metal gate disposed above the composite gate dielectric layer. The method disclosed teaches how to manufacture the FET device.