The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

May. 02, 2019
Applicant:

Universite Catholique DE Louvain, Louvain-la-Neuve, BE;

Inventors:

Jean-Pierre Raskin, Louvain-la-Neuve, BE;

Martin Rack, Louvain-la-Neuve, BE;

Assignee:

UNIVERSITE CATHOLIQUE DE LOUVAIN, Louvain-la-Neuve, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 28/10 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 21/76254 (2013.01);
Abstract

An integrated circuit device includes a semiconductor substrate having a resistivity of at least 100 Ω·cm. An electrically insulating layer contacts the semiconductor substrate. The electrically insulating layer is susceptible of inducing in the semiconductor substrate a parasitic surface conduction layer that interfaces with the electrically insulating layer. An electrical circuit is located on the electrically insulating layer. The electrical circuit includes a section capable of inducing an electrical field in the semiconductor substrate. The integrated circuit device includes a depletion-inducing junction of which at least a portion is comprised in the semiconductor substrate. The depletion-inducing junction can autonomously induce in the semiconductor substrate a depleted zone that interfaces with a section of the electrically insulating layer that lies in-between two sections of the electrical circuit.


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